Phase detectors are utilized in a variety of applications for clock recovery. Typically, phase detectors operate on data transitions. Hence, whenever there is a data transition an error signal is generated. Conventional phase detectors generally operate on either a rising edge of the data signal or on both the rising and falling edges of the data signal. Phase detectors typically generate UP and DOWN signals and are commonly found in conventional phase locked loop (PLL) circuits.
In conventional phase detectors, when the clock signal input to the phase detector leads the data signal rising edge, an UP signal is generated which is narrower than the DOWN signal. When the clock signal lags the data signal rising edge, an UP signal is generated which is wider than the DOWN signal. When the clock signal coincides with the data signal rising edge, the UP and DOWN signals have equal pulse widths. The average of the UP and DOWN signals allows the phase locked loop (PLL) to remain locked.
The correction information of the PLL is essentially contained in the UP pulse. Although the DOWN pulse may appear to have a constant pulse width, it is really a function of the instantaneous frequency of a voltage controlled oscillator (VCO) of the PLL and can vary from cycle to cycle thereby decreasing the capacity of the phase detector to accurately measure the phase error.
A drawback of this implementation is that the net signal (UP-DOWN) contains a high frequency signal component (one full cycle, occurring at the correction rate of the phase detector) that modulates the VCO of the PLL. The effect is a phase jitter on the clock signal (VCO output) known as frequency ripple. This ripple can be reduced by increasing the value of the capacitor (C.sub.1) of a typical loop filter utilized in the PLL (a typical loop filter may consist of a capacitor (C.sub.1) in parallel with a resistor (R) in which R is in series with another capacitor (C.sub.2). Increasing C.sub.1, however, lowers the value of the high frequency pole of the PLL (the high frequency pole is inversely proportional to the RC.sub.1 product) which results in peaking of the phase response of the PLL.
The phase detector also has another drawback--the so called static phase offset. In static phase offset, the clock signal is not centered at the data signal but slightly to the left. When the clock is locked to the data signal in the steady state, the UP signal occurs before the DOWN signal. The UP signal tells the VCO to move forward, causing the clock to shift slightly to the left. Then afterwards, the DOWN signal is generated telling the VCO to move backward. This tends to shorten the negative cycle of the VCO and lengthens its positive cycle. The result is when the rising edge of the clock is used to sample the data signal to recover the data information, the data signal is not sampled in the middle but slightly to the left (depending on the loop filter used). This lowers the jitter tolerance of the PLL.
For many applications such as a token ring network application, the peaking in the phase response is undesirable because of jitter amplification as stations within the network are chained together in a ring configuration. The high frequency ripple on the clock is also undesirable because it introduces unnecessary jitter on the clock signal. The clock signal is used as the timing signal for retransmission of the data in the network. The high frequency ripple reduces the jitter tolerance (or the jitter margin) of the next station in the ring. The high frequency ripple is also accumulated in the ring as jitter causing further transmission problems.
Consequently, a need exists for a phase detector that provides low frequency ripple, alleviates jitter peaking, and provides low static phase offset. The present invention addresses such a need.